1. Field of the Invention
The present invention relates to a phase-change memory device and a method of fabricating the same, and more particularly, to a phase-change memory device in which a phase-change material layer has a multilayered structure with different compositions and a method of fabricating the same.
2. Discussion of Related Art
Semiconductor memories may be categorized as either volatile memories or nonvolatile memories. A volatile memory loses stored data when power supply is interrupted. In contrast, a nonvolatile memory retains stored data even if power supply is abruptly interrupted. With recent advancements in mobile applications such as personal data terminals, the use of nonvolatile memories in various portable devices has markedly increased.
A phase-change random access memory (PRAM) device is an advanced nonvolatile memory device that has lately attracted considerable attention because it exhibits much better operating performance than a flash memory, which is the most widely used nonvolatile memory device at present, and it can easily replace the flash memory in the new era of hyperfine silicon device processes.
The PRAM is fabricated using a phase-change material whose resistance varies according to its crystalline phase. In order to enable a memory operation, the PRAM controls the crystalline state of the phase-change material with application of current or voltage under appropriate conditions to store data, and determines the kind of the stored data based on a variation in resistance according to the crystalline state of the phase-change material. The phase-change material has a low resistance in a crystalline phase and a high resistance in an amorphous phase. For the PRAM, an operation of changing a high-resistance amorphous phase into a low-resistance crystalline phase is referred to as a set operation, while an operation of changing the low-resistance crystalline phase into the high-resistance amorphous phase is referred to as a reset operation.
In order to put PRAMs to practical use, solutions to the following technical issues need to be furnished.
First, power consumption required for driving PRAMs should be reduced. Since a PRAM is driven by controlling the crystalline state of the phase-change material using Joule heat generated due to supply of current to a resistor, it consumes relatively high power. When PRAMs were fabricated using a conventional semiconductor process applied to large-sized devices, too much power and heat for the entire system were generated, so that it was impossible to realize PRAMs with practical operating characteristics.
However, since semiconductor devices have been remarkably scaled down with the continual shrinkage of design scales, it became possible to considerably reduce power consumption required for the operations of PRAMs with currently used design rules of semiconductor processes. However, an operating current required by PRAMs is not yet sufficiently low. In order to commercialize PRAMs as advanced nonvolatile memories, it is necessary to further reduce their operating current.
Second, it is required to further reduce the size of memory cells. In order to successfully replace a flash memory by a PRAM, not only the size of the PRAM but also the size of a memory cell comprised of the PRAM and a transistor device need considerable reduction. A PRAM cell cannot be configured with a PRAM alone; it requires integration of a PRAM and a driving device functioning as a switch for supplying current to the memory device.
In this case, the driving device may be a complementary metal-oxide-semiconductor (CMOS) transistor, a bipolar transistor, or a two-terminal diode. For example, a PRAM cell comprised of a CMOS transistor and a PRAM may have a cell size of about 15 to 20 F2, and a PRAM cell including a bipolar transistor and a PRAM may have a cell size of about 10 to 12 F2. In this case, the PRAM cells have cell sizes even larger than conventional NOR and NAND flash memory cells. Accordingly, in order to strengthen the price competitiveness of PRAMs against flash memories, the cell size of PRAM cells should be reduced to at least about 5 F2.
However, even if the sizes of the PRAM and driving device could be sufficiently reduced by the most advanced semiconductor microfabrication processes, applicability of those processes is greatly limited because conventional PRAMs require excessively large operating currents. It turns out that shrinking the size of memory cells is closely related to reducing their operating currents.
Third, memory devices should be capable of operating at high speed. As explained above, a PRAM employs the reversible transition of a phase-change material between a crystalline phase and an amorphous phase. Transition to a high-resistance amorphous phase is relatively very quick, because it is accompanied by processes of melting and rapidly cooling the phase-change material. In contrast, transition to a low-resistance crystalline phase takes a certain minimum amount of time to crystallize the phase-change material. Accordingly, the phase-change material needs to be crystallized quickly for the PRAM to operate at high speed.
A conventional PRAM may operate at a speed of several tens of ns to several hundred ns, which is much higher than the operating speed of a typical nonvolatile flash memory. However, it is necessary to further increase the operating speed of PRAMs in order to develop advanced integrated PRAMs capable of replacing not only flash memories but also dynamic random access memories (DRAMs) and static random access memories (SRAMs).
Meanwhile, when each device requires an excessively large operating current for a write operation, the number of devices capable of writing data at the same time is reduced. As a result, it is likely to take more time to write needed data in a memory device with a predetermined capacity. Accordingly, it can be seen that improving the operating speed of the PRAM is closely associated with reducing its power consumption.
Finally, the operating reliability of PRAMs needs to be ensured by meeting the following three operating conditions.
First, heat generated during a memory operation of a specific memory device must not destroy or change data stored in an adjacent memory device. In particular, it is highly likely that an interval between devices in highly integrated memory arrays will continue to decrease. In some cases, heat generated during a memory operation of a specific cell may function as noise that hinders a memory operation of an adjacent cell. In a typical memory array operation, this phenomenon is called crosstalk. In the case of a PRAM, a reduction in operating current is advantageous in inhibiting crosstalk and stabilizing operation of a memory array. In other words, the PRAM needs to operate with low power to minimize a rise in the temperature of each memory cell. Accordingly, it is essential to develop a low-power structure in order to ensure reliable memory operations of highly integrated PRAMs.
Second, after data is written in a PRAM, it should be retained as is over time in the operating environment of the PRAM. In other words, set or reset data written in the PRAM should be maintained for a long period of time, even in the high-temperature conditions under which a chip including a memory array actually operates.
Third, even if a PRAM repeats a write operation, data should be stably stored. Although the number of times a PRAM is capable of repeating a write operation is known to be about 108 times, this is optimum data obtained using a test device fabricated under the optimum conditions. Considering deviation in the characteristics of individual memory devices constituting an actual memory array, the number of times a PRAM is actually capable of repeating a write operation is estimated to be about 105 to 107 times. Although the number of times the PRAM is capable of repeating a write operation is larger than the number of times a flash memory is capable of repeating a write operation, it is still too small to develop a new market for embedded memories and advanced integrated nonvolatile memories that will supersede SRAMs and DRAMs.
As described above, technical issues that need solutions in order to enable the practical use of PRAMs are closely connected and cannot be solved separately. In other words, in order to downscale PRAMs and increase their operating speed, their power consumption must be reduced first. Also, when the amount of heat generated during a memory operation is reduced by reducing the operating current of a PRAM, and the volume of a phase-change material required for the memory operation is reduced, the operating reliability of the PRAM may be greatly improved.
Accordingly, in order to put PRAMs to practical use, it is necessary to develop a new PRAM structure that solves all of the problems related to power consumption, device size, operating speed, and operating reliability.